The present invention relates to a pumping voltage regulation circuit; and, more particularly, to a pumping voltage regulation circuit capable of preventing a pumping voltage from being changed depending on the variation of a supply voltage by adjusting a clock signal inputted to a pumping voltage generating circuit through the use of an output signal of a sense amplifier to thereby maintain the pumping voltage to have a preset voltage level.
A flash memory device programs or erases memory cells by using a pumping voltage whose voltage level is higher than that of a supply voltage. The pumping voltage is generated at a pumping voltage generating circuit and regulated to maintain a preset voltage level.
Referring to FIG. 1, there is described a configuration of a conventional pumping voltage regulation circuit. A conventional pumping voltage regulation method will be explained hereinafter with reference to FIG. 1.
A pumping voltage generating circuit 11 receives a clock signal CLOCK from an oscillator and produces a pumping voltage VPPI of about 9 V. This pumping voltage VPPI is used to program or erase flash memory cells. The rise of the pumping voltage VPPI is prevented by a sense amplifier 12 which is provided with a reference voltage Vref and an output voltage of a diode chain 13 consisting of a plurality of diodes connected in series and compares the two voltages supplied thereto. An output signal of the sense amplifier 12 drives an NMOS transistor N11 connected between its output node and a ground node Vss, thereby stabilizing an ascending pumping voltage VPPI. That is, when the reference voltage Vref inputted to the sense amplifier 12 is set to about 1 V, the diode chain 13 is configured to produce an output voltage of about 1 V when a normal pumping voltage of about 9 V is generated. Therefore, in this configuration, if the pumping voltage VPPI is outputted as maintaining about 9 V, the sense amplifier 12 outputs no signal and, thus, the NMOS transistor N11 is not turned on. However, since the output voltage of the diode chain 13 becomes larger than 1 V if the pumping voltage VPPI becomes higher than 9 V, the sense amplifier 12 outputs a certain voltage capable of turning on the NMOS transistor N11, so that there is made an electric path between the output node VPPI and the ground node Vss and, thus, the potential of the output node VPPI becomes lower. Through this operation, the pumping voltage VPPI can maintain the preset voltage level.
However, in the conventional pumping voltage regulation circuit, since the voltage level of the clock signal CLOCK is fixed as the supply voltage Vcc, there occurs a serious overshoot in the pumping voltage level as the supply voltage goes higher. In FIG. 2, there is shown a waveform diagram of the pumping voltage when the clock signal CLOCK having the supply voltage level is inputted to the pumping voltage regulation circuit. Further, since there is employed a method for maintaining the preset pumping voltage by discharging the higher potential than the potential outputted from the pumping voltage generating circuit to the ground node Vss, there may occur a undershoot in the pumping voltage.
Therefore, since it is impossible to produce the pumping voltage maintaining the preset voltage level when generating the pumping voltage by using the conventional circuits, it is difficult to control a threshold voltage of programming or erasing the flash memory cells and, thus, the reliability of the memory device is also deteriorated.
It is, therefore, a primary object of the present invention to provide a pumping voltage regulation circuit capable of generating a preset constant pumping voltage regardless of the variation of a supply voltage.
Another object of the present invention is to provide a pumping voltage regulation circuit for producing a pumping voltage by using a clock signal having a lower voltage level than the supply voltage.
In accordance with the present invention, there is provided a pumping voltage regulation circuit comprising:
a clock adjusting unit for producing a second clock signal according to a combination of a first clock signal and a first control signal or that of the first clock signal and a second control signal;
a pumping voltage generating unit for producing a pumping voltage in response to the second clock signal outputted from the clock adjusting unit;
a diode chain for dividing the pumping voltage; and
a sense amplifier for outputting the second control signal by comparing an output voltage of the diode chain with a reference voltage.